ASNT6111-KMF - Obsolete


ASNT6111-KMF - Obsolete View full size
  • High-speed limiting amplifier with selectable built-in pre-emphasis
  • Four pre-emphasis taps with externally controlled weight and inversion
  • Adjustable data output amplitude and eye quality
  • Single-ended output data eye cross point adjustment
  • Optional main clock frequency multiplier by 2
  • Main clock duty cycle indicators located before and after the multiplier
  • Opposite and parallel adjustment of the main clock and data delays
  • Additional clock input
  • Fully differential CML input and output data, and clock interfaces
  • Selectable main or additional clock at the output with adjustable amplitude
  • CMOS 3-wire interface for digital controls
  • On-chip linear temperature sensor
  • Two power supplies: negative -4.3V and floating positive +3.5V
  • Power consumption: 4.3W
  • Custom CQFP 64-pin package
Function Operating Frequency Power, mW Package
Advanced Driver / Amplifier 1-30 Gbps 4300 64-pin CQFP

DESCRIPTION

Fig.1 Functional Block Diagram

The ASNT6111-KMF SiGe IC shown in Fig. 1 is an advanced programmable driver amplifier (ADA) with built-in 4-tap pre-emphasis. ADA generates a combination of four delayed copies of its input differential data signal dp/dn with certain user-controlled weights and polarities. The copies are created in a 4-bit shift register activated by internal high-speed clock signal (see Sampling Block and Taps). This clock signal is a copy of the main input clock ci0p/ci0n with either matching or doubled frequency. In the multiply-by-2 clock mode, the duty cycles of the input and internal clock signals are monitored and the output duty cycle can be adjusted through external control port phadj (see Clock Multiplier).

 

The part’s I/Os support CML logic interface with on-chip 50Ohm termination to ground. External 50Ohm termination is required. DC-coupling for data and clock output ports is strongly recommended. The input ports can use DC or AC coupling. Amplitude and peaking in the clock and data output signals can be externally adjusted. Both single-ended data output signals also have controlled DC common-mode levels and eye crossing points (see Data Output Buffer). The operational modes of the chip are controlled through a 3-wire serial interface (see 3-Wire Interface Control Block). The chip operates from one negative power supply (positive pin connected to external Ground, negative pin vee = -4.3V) and one floating positive power supply (negative pin connected to vee and positive pin v3p5 = 3.5V). It is recommended to keep the relative deviation of v3p5 from Ground within less than ±0.1V.

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