ASNT7120-KMA


ASNT7120-KMA View full size
  • 18GHz analog input bandwidth
  • Selectable clocking mode: external high-speed clock or internal PLL with external reference clock
  • Broadband operation in external clocking mode: DC-6GS/s
  • On-chip PLL with a central frequency of 10GHz
  • Optional external preset of the internal clock divider
  • Internal demultiplexer 4-to-16 for the output data rate reduction
  • Differential CML input data and clock buffers
  • Proprietary low-power LVDS output interface
  • Selectable output clock frequency and polarity
  • Selectable on-chip digital-to-analog converter for self-testing
  • Single +3.5V power supply
  • Power consumption: 2.4W
  • Custom 100-pin metal-ceramic package
Function Operating Frequency Power, mW Package
6GS/s 4-bit Flash Analog-to-Digital Converter with 18GHz Input Analog Bandwidth DC-18 GHz 2400 100-pin CQFP

DESCRIPTION

Fig. 1 Functional Block Diagram

The ASNT7120-KMA is a 4-bit flash analog to digital converter (ADC) featuring high sampling rate and wide analog front-end bandwidth. The ADC system shown in Fig. 1 includes a linear input buffer (LIB) with a tree architecture and a CML-type input interface with internal 50Ohm single-ended terminations to vcc. The buffer delivers 15 matching copies of the input analog data signal d to the 4-bit flash ADC. The ADC creates 15 samples of the input data in thermometer code, which are then converted into 4-bit binary words with a data rate f. The encoded data is demultiplexed into 16-bit wide words with a data rate f/4 and sent to the output through 16 low-power LVDS buffers. An optional digital-to-analog converter (DAC) can be used for the control of the ADC’s operation.

 

All operations are synchronized by the internal clock multiplication unit (CMU) based on a PLL (phase-locked loop) with an integrated divider. The block can operate in two different modes: clock multiplication (PLL is on) and clock division (PLL is off). In both modes, the divider generates internal clock signals divided by 2, 4, 8, and 16. The generated clocks divided by 4, 8, and 16 are sent to the LVDS output clo through a clock processor that selects the desired speed (cosel1, cosel2 control signals) and polarity (cosel3 control signal) of the output clock. In the second operational mode of CMU, the divider can be preset by the external signal res to ensure the correct phase relation between the output data and clock. The part operates from a single +3.5V power supply, and all external control signals are compatible with the 2.5V CMOS interface.

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