ASNT8052-PQB View full size
  • Programmable clock multiplier (CMU) with two selectable frequency ranges of internal PLL
  • Optional operational mode as a clock divider with PLL disabled
  • Closed-Loop SSB phase noise at 10MHz offset better than 98dB/Hz
  • On-chip Loss-of-Lock control circuit
  • External RC loop filter
  • LVDS, CML, or PECL input reference clock interface
  • Full-rate CML clock input interface
  • Full-rate or half-rate CML clock output interface
  • LVDS divided clock output with optional 90°-step phase adjustment
  • Single +3.3V power supply
  • Low power consumption of 585mW
  • Fabricated in SiGe for high performance, yield, and reliability
  • Standard 40-pin QFN package

Function Operating Frequency Power, mW Package
Programmable PLL w/ Integrated VCOs 11.0-13.3 GHz / 13.0-14.4 GHz 585 40-pin QFN


Fig. 1 Functional Block Diagram

ASNT8052-PQB is a clock multiplication unit (CMU) with a dual-range phase-locked loop (PLL) incorporating high-speed voltage-controlled oscillators (VCOs). The part features several control functions shown in Table 1 within the part's datasheet.


One of the two frequency ranges can be selected by the control signal off12g. In the main operational mode, the IC shown in Fig. 1 accepts a low-speed reference clock cr16p/cr16n with the frequency f/16 and converts it into a high-speed output clock cho with the selectable frequency f or f/2 and a low-speed output clock clo with the frequency f/16. The frequency of the high-speed clock is selected through the external 3-state control signal offcho that can also disable the clock output buffer.


One of four 90° shifted phases of the low-speed output clock with the frequency f/16 can be selected by control signals phs1 and phs2. When operating in the closed-loop mode, the PLL requires an external loop filter connected to pins ftr1p and ftr1n. The output signal loln indicates the locked or unlocked state of the PLL. The PLL also supports an open-loop mode of operation with its selected VCO controlled externally by voltages applied to the filter pins ftr1p and ftr1n. The chip can operate as a divider by 16 of the input high-speed clock cep/cen if the PLL is disabled by the control signal offpll. The part makes use of a single +3.3V power supply and is characterized for operation from −25°C to 125°C of junction temperature.

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