ASNT8131-PQC View full size
  • Wide frequency range from DC to 32GHz
  • Divided-by-2 and divided-by-4 outputs
  • 50% duty cycle of the divided clock signals
  • Fully differential CML input interface
  • Fully differential CML output interfaces
  • Single +3.3V or -3.3V power supply
  • Industrial temperature range
  • Power consumption of 317mW at full operational speed
  • Standard MLF/QFN 24-pin package

Function Operating Frequency Power, mW Package
High-Sensitivity Clock Divider by-2 / by-4 DC-32 GHz 317 24-pin QFN


Fig. 1 Functional Block Diagram

ASNT8131-PQC is a high-speed, low-power divider by-2 and by-4 with increased sensitivity. The part shown in Fig. 1 accepts a CML input clock signal (cp/cn) with the speed from DC to maximum operational frequency and provides clean 50% duty cycle output signals with divided-by-2 (c2p/c2n) and divided-by-4 (c4p/c4n) frequency. The part’s I/Os support the CML logic interface with on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination. It operates from a single +3.3V or -3.3V power supply.

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