ASNT1017-PQA


ASNT1017-PQA View full size
  • Programmable serializer 16-to-1 with CMU or digital operational modes
  • Supports data rates from 12.0Gbps to 14.3Gbps in CMU mode and DC to 17Gbps in digital mode
  • LVDS compliant input data buffers
  • Selectable full-speed or divided-by-2 clock output
  • LVDS output clock-divided-by-16 with a selectable phase
  • Single +3.3V power supply
  • Industrial temperature range
  • Low power consumption of 500mW at maximum speed
  • Standard 100-pin QFN package (12mm x 12mm)

Function Operating Frequency Power, mW Package
16:1 Multiplexer with 12.0-14.3GHz Integrated CMU // Digital 16:1 Multiplexer 12-14.3 Gbps / DC-17 Gbps 500 100-pin QFN

DESCRIPTION

Fig. 1 Functional Block Diagram

ASNT1017-PQA is a low power and high-speed 16-to-1 programmable multiplexer (MUX) with an internal clock multiplier unit (CMU) that can also operate in the digital mode using an external high-speed clock. The main function of the chip shown in Fig. 1 is to multiplex 16 parallel data channels running at a bit rate of fbit/16 into a high-speed serial bit stream running at fbit. It provides a high-speed output data channel for point-to-point data transmission over a 50Ω controlled impedance media. The transmission media can be a printed circuit board or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation characteristics of the transportation media and the degree of noise coupling to the signaling environment.

 

During normal operation, the serializer’s low-speed input buffer LS DIBx16 accepts external 16-bit wide parallel data words d00-d15 through 16 differential LVDS inputs and delivers them to the multiplexer’s core MUX16:1 for serialization. By utilizing the pin bitorder, the serializer can designate either d00 or d15 as the MSB (first output serial bit), thus simplifying the interface between the multiplexer and a digital data processor. MUX16:1 utilizes multiple divided down clock signals that are generated from the full rate clock C by the internal divider /16. The divider also produces the half rate clock C2 for the high speed clock output buffer HS COB and the divided-by-16 clock signal C16 for use by the phase-locked loop PLL.

 

In PLL mode, the clock signal C is synthesized by the PLL which locks the internal signal C16 to the external system-level clock cr16 delivered through the low speed clock input buffer LS CIB. The cr16 frequency may be selected as either 1/16 or 1/64 of the frequency of the activated VCO (voltage-controlled oscillator) in the PLL. The PLL contains 2 full rate VCOs to cover the required frequency range. One of the VCOs can be selected utilizing the off12g control pin. The PLL also generates a loss-of-lock alarm signal lol1n. In digital mode, the PLL is disabled and the external signal ce delivered through the high-speed clock input buffer HS CIB is used as clock signal C.

 

The serialized words generated by MUX16:1 are transmitted as binary signals qcml by the differential CML output buffer Data OB. The selectable full-rate or half-rate clock cho is transmitted by a similar CML buffer (HS COB) in parallel with the high-speed data. The clock and data outputs are well phase-matched to each other resulting in a very little relative skew over the operating temperature range of the device. HS COB may be disabled or its operational mode changed by means of the 3-state (vee, vcc, not connected) CMOS signal offcho. Both output stages are back terminated with on-chip 50Ω resistors.

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