ASNT2016-PQA


ASNT2016-PQA View full size
  • 1:16 demultiplexer (DMUX) with integrated full rate CDR (clock and data recovery).
  • Supports multiple data rates in the 11.3-12.5Gbps range in the CDR mode.
  • Can operate in broadband digital mode up to 12.5Gbps with application of full rate clock.
  • Supports both RZ and NRZ input data formats.
  • LVDS output data buffers that feature a low-power proprietary architecture.
  • Stable clock-divided-by-16 LVDS output with 90°-step phase selection.
  • Supports clock-divided-by-16/64 input reference clock.
  • Single +3.3V power supply.
  • Industrial temperature range.
  • Low power consumption of 730mW at 12.5Gbps.
  • Available in standard 100-pin QFN package (12mm x 12mm).

Function Operating Frequency Power, mW Package
1:16 Demultiplexer with Integrated Full Rate CDR // Digital 1:16 Demultiplexer 11.3-12.5 Gbps / DC-17 Gbps 730 100-pin QFN

DESCRIPTION

Fig. 1. Functional Block Diagram

ASNT2016-PQA is a 12.5Gbps 1:16 deserializer (DMUX) with full rate integrated clock and data recovery (CDR FWD). The DMUX can cover input data rates (fbit) in the CDR mode from 11.3Gbps to 12.5Gbps by utilizing its on-chip full-rate VCO or function in the broadband digital mode. An external full clock “ce” must be applied to the high speed CML clock input buffer (HS CIB) for digital operation. Selection of the operational mode is made through pin “offcdr”.

 

The main function of ASNT2016-PQA is to demultiplex a serial input data channel “d” running at a bit rate of fbit into 16 parallel data channels “q00-q15” running at a bit rate of fbit/16. The high sensitivity CDR FWD block ensures accurate clock and data recovery for input data signal amplitudes greater than 20mV peak to peak (p-p) differential or single-ended. This is accomplished with the CDR FWD circuitry incorporating both a phase and frequency acquisition loop to recover a full rate clock “C” from the input data stream. This recovered clock samples the input data bits before they are demultiplexed and is also sent to the internal divider (/16). The application of an external low speed system clock “cr” running at 1/16 or 1/64 the frequency of the VCO clock through the low speed clock input buffer (CLK IB) is required for CDR FWD to operate correctly. CLK IB by default provides a LVDS input interface, but can properly process input CML signaling through utilization of the “oncml” control signal. Pin “oncr16” selects between direct “cr” and “cr” post the divider-by-4 (/4) block. 


The high-speed CML data input buffer (Data IB) and HS CIB provide on-chip 50Ω termination and are designed to be driven by devices with 50Ω source impedance. Data IB sets its termination voltage internally, but “vtt” can be used to externally adjust it if desired. Pins “off0” control the offset voltage between Data IB’s “dp” and “dn” inputs allowing the user to change the slicing or threshold level at the serial data input. A peak detector is incorporated in Data IB to monitor the amplitude of the incoming data stream with its output made available through the differential pins “sld”. Data IB can handle both RZ and NRZ input data formats.

 

The reconstructed serial input data is latched into the demultiplexer (DMX1:16) and is subsequently deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed parallel words. Utilizing pin “bitordn”, the deserializer can designate either “q00” or “q15” as the MSB thus simplifying the interface between ASNT2016 and a following ASIC.  

 

Sixteen proprietary low-power LVDS output data buffers (LVDS DOBx16) are used to deliver the 16 data output signals “q00-q15” while a similar dual LVDS clock output buffer (LVDS COBx2) outputs the two low-speed clock signals “clm” and “clo”. The buffers satisfy all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 while only consuming 30mW each. The phase of “clo” can be modified by 90° increments by utilizing pins “phs1” and “phs2”, which program the clock processing block (CLK Proc).

 

ASNT2016-PQA includes alarm indicators loss of signal “losn” and loss of lock “loln”. “offrz” must be activated when NRZ data is present for proper “losn” alarm generation. Off chip passive filter components are required by CDR FWD and are connected through pins “ftr1/2”. The deserializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C of junction temperature.

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