ASNT2110-KMF View full size
  • 1:2 demultiplexer (DMUX) with integrated full-rate CDR
  • CDR range from 25.5GHz to 32.5GHz covered by 3 selectable VCOs
  • Digital operational mode with DC to 32.5GHz external clock
  • RZ and NRZ input data formats
  • Adjustable time of data sampling point for optimum BER performance
  • CML compliant differential input and output high-speed data and clock interfaces
  • LVDS compliant input reference clock interface
  • Full rate clock and retimed data output available for 1:1 CDR operation
  • Half rate data outputs with toggle synchronization functionality
  • Signal inversion and muting capabilities in all output buffers
  • Single +3.3V or -3.3V power supply
  • Low power consumption of 1.6W at the maximum operational speed
  • Industrial temperature range
  • Custom CQFP 64-pin package

Function Operating Frequency Power, mW Package
Reconfigurable 1:2 Demultiplexer with Integrated Half Rate PAM4 CR 25.5-32.5 GHz 1600 64-pin CQFP


Fig. 1. Functional Block Diagram

ASNT2110 is a 1:2 demultiplexer (DMUX) with full-rate integrated clock and data recovery (CDR). The IC shown in Fig. 1 can function in either CDR mode covering a wide range of input data rates (fbit) by utilizing its three on-chip VCOs (voltage-controlled oscillators), or in a broadband digital mode. Selection of the desired working data rate and mode is accomplished through pins vcos0 and vcos1 (see Table 1). An external low speed system clock c32p/c32n running at 1/32 the frequency of the active VCO must be applied to the low-speed LVDS clock input buffer (CLK IB) in CDR mode. An external full-rate clock cep/cen must be applied to the high speed CML clock input buffer (HS CIB) for digital operation.


The main function of the chip is to convert a RZ or NRZ input data signal dp/dn with a bit rate of fbit accepted by CML buffer (Data IB) into 2 parallel NRZ data signals q0p/q0n and q1p/q1n running at bit rates of fbit/2 and delivered to the outputs by CML data output buffers (D2OBx2). The clock and data are recovered from the input data stream by the CDR. The phase of the clock recovered by the CDR can be adjusted externally through pin phshft to locate the optimum data sampling point and achieve the lowest system bit error rate (BER).


A full rate retimed NRZ data output signal dop/don is also available through the CML data output buffer (DOB) allowing the part to be used as a 1:1 CDR. Half rate clock c2p/c2n delivered through the CML clock output buffer (COB) has a tight phase alignment to demultiplexed data output signals q0p/q0n and q1p/q1n. Data IB can operate with differential or single-ended input signals. It includes tuning pins dcinp/dcinn for DC offset of the input signals in case of AC termination. When the buffer is operating with a DC-terminated single ended input signal, a correct threshold voltage should be applied to the unused input pin. A peak detector is also included to provide means of demodulating AM components carried by the input data with frequency ranges of up to a few hundred KHz. The peak detector’s output signal is delivered to differential port pkdtp/pkdtn. All CML I/Os provide on chip 50Ω termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination. Output buffers DOB, COB, and D2OBx2 can be individually disabled through pins ondo, onco, and ond2o to save power.

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