ASNT2112-KMF


ASNT2112-KMF View full size
  • 1:2 demultiplexer (DMUX) with integrated full-rate CDR
  • CDR range from 21GHz to 26GHz covered by 3 selectable VCO
  • Digital operational mode with DC to 26GHz external clock
  • Supports RZ and NRZ input data formats.
  • Adjustable time of data sampling point for optimum BER performance
  • CML compliant differential input and output high-speed data and clock interfaces
  • LVDS compliant input reference clock interface
  • Full rate clock and retimed data output for 1:1 CDR operation
  • Half rate data outputs with toggle synchronization functionality
  • Signal inversion and muting capabilities in all output buffers
  • Single +3.3V or -3.3V power supply
  • Low power consumption of 1600mW at 25Gbps
  • Industrial temperature range
  • Custom CQFP 64-pin package

Function Operating Frequency Power, mW Package
Reconfigurable 1:2 Demultiplexer with Integrated Half Rate PAM4 CR 21-26 GHz 1600 64-pin CQFP

DESCRIPTION

Fig. 1. Functional Block Diagram

ASNT2112-KMF is a 1:2 demultiplexer (DMUX) with full-rate integrated clock and data recovery (CDR). It can function in CDR mode covering a wide range of input data rates (fbit) by utilizing its three on-chip VCOs (voltage-controlled oscillators), or in a broadband digital mode. Selection of the desired working data rate and mode is accomplished through pins “vcos0” and “vcos1”. An external low speed system clock “c32p/n” running at 1/32 the frequency of the active VCO must be applied to the low-speed LVDS clock input buffer (CLK IB) in CDR mode. An external full-rate clock “cep/n” must be applied to the high speed CML clock input buffer (HS CIB) for digital operation.

 

The main function of ASNT2112-KMF is to convert RZ or NRZ input data signal “dp/n” with a bit rate of fbit accepted by CML buffer “Data IB” into 2 parallel NRZ data signals “q0p/n” and “q1p/n” running at bit rates of fbit/2 and delivered to the outputs by CML data output buffers (D2OBx2). The clock and data are recovered from the input data stream by CDR. The phase of the clock recovered by CDR can be adjusted externally through pin “phshft” to locate the optimum data sampling point to achieve the lowest system bit error rate (BER). A full rate retimed NRZ data output signal “dop/n” is also available through the CML data output buffer (DOB) allowing the part to be used as a 1:1 CDR. Half rate clock “c2p/n” delivered through the CML clock output buffer (COB) has tight phase alignment to demultiplexed data output signals “q0p/n” and “q1p/n”. It operates on a single +3.3V or -3.3V power supply and is characterized for operation from 0°C to 125°C of junction temperature.

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