ASNT2031-MBL View full size
  • 24:48 digital demultiplexer (DMUX) with SSTL1.5 input and output interfaces.
  • Supports data rates from 1.0Mbps to 2.0Gbps.
  • User-controllable independent internal delays for data and clock signals.
  • 1.5V  I2C control interface with a user-defined 3-bit chip address.
  • Preset function for synchronization of multiple parallel devices.
  • Full-rate output copy of external high-speed clock input signal.
  • Two pairs of clock divided-by-2 and synchronous clock enable outputs for supporting the tree-type demultiplexation structure.
  • Additional synchronous clock divided-by-4 output.
  • Dual power supply of +3.0V and +1.5V.
  • Industrial temperature range.
  • Low power consumption of 2.1W at 2.0Gbps.
  • Available in custom 256-pin BGA package (13mm x 13mm x 2.5mm).

Function Operating Frequency Power, mW Package
24:48 SSTL-SSTL Demultiplexer 1.0Mbps-2.0 Gbps 2100 256-pin BGA


Fig. 1. Functional Block Diagram

ASNT2031-MBL is a broad-band 1.0Mbps-to-2.0Gbps multi-channel digital deserializer-demultiplexer (DMUX) 24-to-48 with external initial preset functionality and 1.5V single-ended SSTL1.5 input and output interfaces for data and preset signals, as well as matching differential interfaces for clock signals.


The part includes active variable delay lines (DelLine) in each input data and clock path for accurate signal alignment at the DMUX register inputs in order to define the optimal sampling point for the input data signals (“data in”). The value of each delay is externally controlled through an I2C interface with a user-selectable 3-bit chip address.


The operational speed of DMUX is defined by an external clock signal (“clk in”) that is converted into the required timing signals by an internal divider and is also supplied to the output of the chip (“clk out”). The divider can be preset to a certain initial state by the external clock enable signal (“clken in”), which allows synchronization of multiple DMUX devices operating in parallel.

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