About Us

ADSANTEC is a privately held company, headquartered in Torrance, CA, USA. We provide ultra high-speed and high- frequency ICs, Full Test Solutions, Instrumentation, and Custom ASIC Design Solutions to many Tier 1 and Tier 2 companies. Since our inception in 2002, we have been awarded 25 SBIR contracts and developed over 200 Chips, Boards and Instruments. The company has over 50 US and international patents.


The ADSANTEC Team consists of industry pioneers and veterans. With 20 members on board, 3 hold Ph.D.s and 8 hold M.S. Degrees in Electrical Engineering.


Vladimir Katzman, Ph.D.


Dr. Katzman received his M.Sc. in Electrical Engineering (1971) and Ph.D. in Electronics (1984) at the Kaunas Technical University (KTU), Kaunas, Lithuania. His studies concentrated on digital signal processing and communication networks.

In 1974, Dr. Katzman started to work at the Vilnius Scientific Research Institute developing equipment for the ASIC testing. In 1987, he became a founder and a director of the Lithuanian Radio Electronics and Ecology Research Institute developing advanced technologies in areas of electronics and environmental protection, utilizing advanced biological sensors technology. In 1993-96, Dr. Katzman worked at the Physical Optics Corporation in Torrance, CA, where he successfully completed several Government SBIR contracts (3 Phase I and 2 Phase II projects). Between 1996 and 2002, Dr. Katzman served as Vice President of Engineering at Multilink Technology Corporation, Somerset, NJ. At Multilink, he was responsible for the development of standard and custom products for terrestrial and submarine communications. Dr. Katzman holds over 50 U.S. and international patents.

Dr. Katzman started ADSANTEC in 2002 focusing his efforts on designing IC solutions for ultra-high speed backplane applications, based on novel multi-level interconnect techniques (patent pending).

Vladimir Bratov, Ph.D.

Vice President

Dr. Bratov received his M.S. (1976) and Ph.D. in Electronics (1991) at the Moscow Institute of Electronic Technology (MIET), Russia. In 1976-98, Dr. Bratov worked as Lead Design Engineer and Lecturer at the MIET. During that time he has taught a number of courses in semiconductor device physics, IC design, and modern IC testing. He has also served as a part-time consultant for the 13th Research Institute of Ministry of Electronics Industry (Hebei, P.R. China), Middlesex University Microelectronics Centre (London, UK), and Samsung Electronics Co. (Moscow, Russia).

From 1999 to 2003, Dr. Bratov served as Senior Design Engineer and Design Group Leader at Multilink Technology Corporation, Somerset, NJ. His responsibilities included schematic and physical design of SERDES products with CML, LVDS, PECL, LVTTL and LVCMOS interfaces. While at Multilink, he has also developed special software for circuit optimization and Cadence-based software for layout design automation, both utilizing proprietary algorithms.

Since 2003, Dr. Bratov has served as Vice President of Engineering at ADSANTEC. His responsibilities include leading the design of custom ICs for research, Government SBIR contracts, and commercial applications. Dr. Bratov serves as a Principal Investigator on two Phase II SBIR contracts for the US Department of Energy and the US Air Force, and one Phase I program for NASA. Dr. Bratov holds over 10 U.S. and international patents.

Jeb Binkley, M.S.

Director, Mixed Signal IC Design

Mr. Binkley received his B.S. in Electrical Engineering (1999) from Cornell University, and his M.S. in Electrical Engineering (2004) from the University of Southern California (USC). He is currently working towards his Ph.D. in Electrical Engineering at USC with a concentration in adaptive mixed-signal circuitry under the guidance of Prof. Choma.

From 1999 to 2002, Mr. Binkley worked as an IC Design and Test Engineer at the Santa Monica, CA, division of Multilink Technology Corporation. While at Multillink, Mr. Binkley designed and tested several test chips with operational speeds up in the 50GHz frequency range. His designs included a 4:1 multiplexer, a PRBS generator, and a static frequency divider. Mr. Binkley worked with many different IC fabrication technologies including SiGe, GaAs, and InP.

Since 2003, Mr. Binkley has worked at ADSANTEC as a Mixed-Signal ASIC Design Group Leader. He has worked on and completed several SBIR Phase I and II programs. His responsibilities include IC R&D in analog-to-digital converters, radiation hard circuitry, and adaptive mixed signal circuitry, proposal/report writing. Mr. Binkley has made several government meeting and conference presentations.

 SBIR Programs

“Scalable IDS Algorithm for Rapid Detection of Internal Attacks” from US Army

Phase I (1/2003-7/2003)

Phase II (11/2003-03/2006)

POC: Robin Stoltz, Ph. 301-394-3381.

“Ternary SERDES for Intra-System Data Transfer” from NASA

Phase I (1/2003-7/2003)

POC: Frederick T. Little, Ph. 301 286-0888.

“Ultra-Fast ADC with Ternary Digital Output” from DOE

Phase I (7/2003-4/2004)

Phase II (07/2004-07/2006)

POC: Dr. Jehanne Simon-Gilo, Ph. 301 903-1455.

“Robust Adaptive Spatial-Temporal Algorithms for Clutter Rejection and Scene stabilization” from MDA

Phase I (7/2003-1/004)

Phase II (7/2004-7/2006)

POC: James Brown Ph. 781 377-4412.

“Switching Fabric based on Multi-Level LVDS Compatible Interconnect” from NASA

Phase I (1/2004-7/2004)

Phase II (12/20/04)

POC: Mayra Nieves-Torres Ph. 301-286-4242.

“Radiation-hardened Multi-channel Programmable Voltage Level Converter” from US Air Force

Phase I (4/2004-1/2005)

Phase II (4/2005-4/2007)

POC: Jeannie Barnes Ph. 505-846-4695.

Conference Proceedings

Universal Input Buffer for Programmable Logic Devices

Authors: V. Bratov, J. Binkley, V. Katzman, A. Bratov, A. Otero, G. Rakow

Publication: 9th MAPLD International conference, Washington, DC, September 26-28, 2006.

Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

Authors: V. Bratov, J. Binkley, V. Katzman, and J. Choma

Publication: IEEE Trans. on Circuits and Systems I, v. 53, No. 10, Oct. 2006, pp. 2101-2108


Method And System For Multilevel Serializer/Deserializer

U.S. Patent No. 7,342,520, March 11, 2008.

Anti-See Protection Techniques For High-Speed Ics With A Current-Switching Architecture

U.S. Patent Application Approved

LVDS Standard I/O Buffers: PDF

Full SiGe 120 GHz CML Component Library: PDF