SBIR Programs


“Scalable IDS Algorithm for Rapid Detection of Internal Attacks” from US Army; Phase I (1/2003-7/2003); Phase II (11/2003-03/06); POC: Robin Stoltz, ph. 301-394-3381.


“Ternary SERDES for Intra-System Data Transfer” from NASA; Phase I (1/2003-7/2003); POC: Frederick T. Little, Ph. 301 286-0888.


“Ultra-Fast ADC with Ternary Digital Output” from DOE; Phase I (7/2003-4/2004); Phase II from (07/2004-07/2006); POC: Dr. Jehanne Simon-Gilo, ph. 301 903-1455.


“Robust Adaptive Spatial-Temporal Algorithms for Clutter Rejection and Scene stabilization” from MDA; Phase I (7/2003-1/004); Phase II from (7/2004-7/2006); POC: James Brown ph. 781 377-4412.


“Switching Fabric based on Multi-Level LVDS Compatible Interconnect” f from NASA; Phase I (1/2004-7/2004); Phase II from 12/20/04; POC: Mayra Nieves-Torres ph. 301-286-4242.


“Radiation-hardened Multi-channel Programmable Voltage Level Converter” from US Air Force; Phase I (4/2004-1/2005); Phase II (4/2005-4/2007); POC: Jeannie Barnes ph. 505-846-4695.




Conference Proceedings


Universal Input Buffer for Programmable Logic Devices

Authors: V. Bratov, J. Binkley, V. Katzman, A. Bratov, A. Otero, G. Rakow

Publication: 9th MAPLD International conference, Washington, DC, September 26-28, 2006.


Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

Authors: V. Bratov, J. Binkley, V. Katzman, and J. Choma

Publication: IEEE Trans. on Circuits and Systems I, v. 53, No. 10, Oct. 2006, pp. 2101-2108






Method And System For Multilevel Serializer/Deserializer

U.S. Patent No. 7,342,520, March 11, 2008.


Anti-See Protection Techniques For High-Speed Ics With A Current-Switching Architecture

U.S. Patent Application Approved


LVDS Standard I/O Buffers: PDF


Full SiGe 120 GHz CML Component Library: PDF

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