ASNT1012 (ASNT1032)

• 16 to 1 multiplexer (MUX) with integrated CMU (clock multiplication unit)
• Supports multiple data rates in the 9.8-12.5Gb/s range
• LVDS compliant input data buffers
• Clock-divided-by-16 LVDS output buffer
• Single +3.3V power supply
• Industrial temperature range
• Low power consumption of 660mW at 12.5Gbps
• Available in standard 100-pin QFN package (12mm x 12mm)

ASNT1012 is a low power and high-speed 16 to 1 multiplexer (MUX) with an internal clock multiplier unit (CMU). The MUX can function at data rates (fbit) between 9.8Gbps to 12.5Gbps by utilizing its multiple on-chip full-rate VCOs.

The main function of ASNT1012 is to multiplex 16 parallel data channels running at a bit rate of fbit/16 into a high speed serial bit stream running at fbit. It provides a high-speed output data channel for point-to-point data transmission over a controlled impedance media of 50Ohm. The transmission media can be a printed circuit board or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation characteristics of the transportation media and the degree of noise coupling to the signaling environment.

During normal operation, the serializer’s low-speed input buffer (LS DIBx16) accepts external 16-bit wide parallel data words “d00”-“d15” through 16 differential LVDS inputs and delivers them to the multiplexer’s core (MUX16:1) for serialization. By utilizing pin “bitorder”, the serializer can designate either “d00” or “d15” as the MSB thus simplifying the interface between ASNT1012 and a proceeding ASIC.

MUX16:1 serializes the data words with multiple divided down clock signals that are generated from the full rate clock “C” by the internal divider (/16). The divider also produces half rate clock “C2” for the high speed clock output buffer (HS COB), and engenders a full rate clock divided-by-16 signal “C16” for use by the PLL (PLL). “C” is synthesized by PLL, which locks “C16” to the external system level clock “cr16” that is provided by the low speed clock input buffer (LS CIB). “cr16” must be 1/16 the frequency of the active full rate VCO in PLL. PLL contains 2 full rate VCOs to cover the 9.8-12.5GHz range, which are selected utilizing the “off12g” control pin.

The serialized words are transmitted as 2-level signals “qcml” by a differential CML output buffer (Data OB). A full-rate or half-rate clock “cho” is transmitted by a similar CML buffer (HS COB) in parallel with the high-speed data. The clock and data outputs are well phase matched to each other resulting in very little relative skew over the operating temperature range of the device. HS COB may be disabled or its operational mode changed by means of the 3-state (vee, vcc, not connected (n/c)) CMOS “offcho” signal. Both output stages are back terminated with on-chip 50Ohm resistors.

ASNT1012 also provides a differential low speed output clock “clo” though a LVDS clock output buffer (LVDS COB). PLL generates a loss of lock signal alarm “lol1n”. An off chip capacitor is required for PLL and is connected through pins “ftr1p/n”. The serializer uses a single +3.3V power supply and is characterized for operation from −25°C to 125°C of junction temperature.

LS DIBx16

The Low-Speed Data Input Buffer (LS DIBx16) consists of 16 proprietary universal input buffers (UIBs) that exceed the LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is designed to accept differential signals with amplitudes above 60mV peak-to-peak (p-p), DC common mode voltage variation between the negative (vee) and positive (vcc) supply rails, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes above 60mV p-p and threshold voltages between vee and vcc. The input termination impedance is set to 100Ohm differential.

LS CIB

The Low-Speed Clock Input Buffer (LS CIB) is a UIB that can run at a frequency up to 800MHz. This block is used to deliver the low speed system clock “cr16” as a reference signal to PLL.

PLL

The Phase Locked Loop (PLL) contains a phase frequency detector, charge pump, an on-chip integrator with an additional off-chip filter connected between the pins “ftr1p” and “ftr1n” (Fig. 2), and two selectable LC-tank VCOs centered at 11.8GHz and 11.0GHz. The main function ofPLL is to synthesize full rate clock “C” by aligning the phase and frequency of “C16” of the activated VCO to the externally applied system clock “cr16”. A logic “0” output CMOS loss-of-lock “lol1n” alarm signal is generated by PLL if its two input clock signals are not matching in phase and/or frequency.

Selection of the different VCOs of PLL is achieved by utilizing the CMOS control pin “off12g”. A logic “1” chooses the 11.0GHz VCO while a logic “0” selects the 11.8GHz VCO (default state). The unused VCO is turned completely off in order to save power.

/16

The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. High-speed clock “C” is fed into the first divide-by-2 circuit that generates “C2”. “C2” is routed internally to the next divide-by-two circuit and outside of the block to MUX16:1 and HS COB. Other divided down clock signals are formed and routed to MUX16:1 in similar fashion. “C16” is passed on to PLL and LVDS COB to become the output low speed clock signal “clo”.

MUX16:1

The 16 to 1 Multiplexer (MUX16:1) utilizes a tree type architecture that latches the incoming data on the negative edge of the “C16” clock signal that is supplied by /16. The 16-bit wide data word is subsequently multiplexed and delivered to Data OB as a serial data stream running at a data rate up to 12.5Gbps. The latency of this circuit block is equal to roughly one period of the low-speed input clock. When “bitorder”=0 (default), “d00”is the MSB and when “bitorder”=1, “d15” is designated the MSB.

Data OB

The Data Output Buffer (Data OB) receives high-speed serial data from MUX16:1 and converts it into the CML output signal “qcml” with a single ended swing of 600mV. The buffer requires 50Ohm external termination resistors connected between “vcc” and each output to match its internal 50Ohm resistors and can operate at a data rate up to 12.5Gbps.

HS COB

The High Speed Clock Output Buffer (HS COB) utilizes the same termination scheme as Data OB and can operate at a frequency up to 12.5GHz while producing a single-ended CML output swing of 600mV. The buffer can be enabled or disabled by the external 3-state (vcc, vee, not connected (n/c)) control signal “offcho”. The n/c default state corresponds to a “C2” output signal. The logic “0” state provides a full-rate clock output signal while the logic “1” state disables the buffer completely to save power.

LVDS COB

The LVDS Clock Output Buffer (LVDS COB) receives “C16” from /16 and converts it into a LVDS output signal “clo”. The proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at frequencies up to 2GHz with a low power consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.

Output Timing

Phase relation between the output data “qcml” and full rate output clock “cho” is specified in Table 1 and illustrated by Fig. 3.

Pins diagram for asnt1012-asnt1032 is not available.

The chip is packaged in a standard 100-pin QFN package.

Full package description: PDF

Full product description: PDF