ASNT2011A (ASNT2015)

• 1:16 demultiplexer (DMUX) with integrated full rate CDR (clock and data recovery)
• Supports multiple data rates in the 11.3-12.5Gbps range in the CDR mode
• Can operate in broadband digital mode up to 12.5Gbps with application of full rate clock
• Supports both RZ and NRZ input data formats
• LVDS output data buffers that feature a low-power proprietary architecture
• Stable clock-divided-by-16 LVDS output with 90°-step phase selection
• Supports clock-divided-by-16/64 input reference clock
• Single +3.3V power supply
• Industrial temperature range
• Low power consumption of 730mW at 12.5Gbps
• Available in standard 100-pin QFN package (12mm x 12mm)

ASNT2016 is a 12.5Gbps 1:16 deserializer (DMUX) with full rate integrated clock and data recovery (CDR FWD). The DMUX can cover input data rates (fbit) in the CDR mode from 11.3Gbps to 12.5Gbps by utilizing its on-chip full-rate VCO or function in the broadband digital mode. An external full clock “ce” must be applied to the high speed CML clock input buffer (HS CIB) for digital operation. Selection of the operational mode is made through pin “offcdr”.

The main function of ASNT2016 is to demultiplex a serial input data channel “d” running at a bit rate of fbit into 16 parallel data channels “q00-q15” running at a bit rate of fbit/16. The high sensitivity CDR FWD block ensures accurate clock and data recovery for input data signal amplitudes greater than 20mV peak to peak (p-p) differential or single-ended. This is accomplished with the CDR FWD circuitry incorporating both a phase and frequency acquisition loop to recover a full rate clock “C” from the input data stream. This recovered clock samples the input data bits before they are demultiplexed and is also sent to the internal divider (/16).

The application of an external low speed system clock “cr” running at 1/16 or 1/64 the frequency of the VCO clock through the low speed clock input buffer (CLK IB) is required for CDR FWD to operate correctly. CLK IB by default provides a LVDS input interface, but can properly process input CML signaling through utilization of the “oncml” control signal. Pin “oncr16” selects between direct “cr” and “cr” post the divider-by-4 (/4) block.

The high-speed CML data input buffer (Data IB) and HS CIB provide on-chip 50Ohm termination and are designed to be driven by devices with 50Ohm source impedance. Data IB sets its termination voltage internally, but “vtt” can be used to externally adjust it if desired. Pins “off0” control the offset voltage between Data IB’s “dp” and “dn” inputs allowing the user to change the slicing or threshold level at the serial data input. A peak detector is incorporated in Data IB to monitor the amplitude of the incoming data stream with its output made available through the differential pins “sld”. Data IB can handle both RZ and NRZ input data formats.

The reconstructed serial input data is latched into the demultiplexer (DMX1:16) and is subsequently deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed parallel words. Utilizing pin “bitordn”, the deserializer can designate either “q00” or “q15” as the MSB thus simplifying the interface between ASNT2016 and a following ASIC.

Sixteen proprietary low-power LVDS output data buffers (LVDS DOBx16) are used to deliver the 16 data output signals “q00-q15” while a similar dual LVDS clock output buffer (LVDS COBx2) outputs the two low-speed clock signals “clm” and “clo”. The buffers satisfy all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 while only consuming 30mW each. The phase of “clo” can be modified by 90° increments by utilizing pins “phs1” and “phs2”, which program the clock processing block (CLK Proc).

ASNT2016 includes alarm indicators loss of signal “losn” and loss of lock “loln”. “offrz” must be activated when NRZ data is present for proper “losn” alarm generation. Off chip passive filter components are required by CDR FWD and are connected through pins “ftr1/2”.

The deserializer uses a single +3.3V power supply and is characterized for operation from -25°C to 125°C of junction temperature.

Data IB

The Data Input Buffer (Data IB) can process an input CML data signal “d” with bit rates up to 12.5Gbps in either the RZ or NRZ format. Data IB can also accept a single-ended signal to one of its input ports “dp” or “dn” with a threshold voltage applied to the opposite tuning pin “off0n” or “off0p”. The tuning pins have input impedances of 250Ohm and allow the user to change the slicing level before the data is sampled by the recovered clock. Data IB can handle input signal amplitudes between 20mV and 600mV p-p differential or single-ended. The buffer utilizes on-chip single-ended termination of 50Ohm to “vtt”=2.5V (default) for each input line where “vtt” can be adjusted externally.

Also included in Data IB is an input signal peak detector that delivers its response through the output differential signal “sld”. The detector can demodulate AM component(s) carried by the input data stream that are in the frequency range of up to a few hundred kHz. The peak detector’s output impedance is 3.2KOhm single ended to Vcc.

CLK IB

The Clock Input Buffer (CLK IB) consists of a single proprietary universal input buffer (UIB). UIB is designed to accept differential signals with amplitudes higher than 60mV p-p, DC common mode voltage variation between the negative (vee) and positive (vcc) supply voltages, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of more than 60mV p-p and threshold voltages between vee and vcc. By default, the input termination impedance is set to 100Ohm differential to support the LVDS standard. Correct impedance for the CML standard (50Ohm single ended to vcc) is set by applying logic “1” to “oncml”.

/4

The divide-by-4 block (/4) is controlled by “oncr16” and is activated when “cr” is equal to the frequency of “C16”. “oncr16” should be set to logic “0” (default) when “cr” is 1/4 the frequency of “C16”. In both cases, a reference clock signal is delivered to CDR FWD with a frequency of 1/64 the rate of “C”.

HS CIB

The High-Speed Clock Input Buffer (HS CIB) can process an external CML clock signal “ce” with frequencies from 10.0MHz to 12.5GHz. It can also accept a single-ended signal to “cep/cen” with a threshold voltage applied to the unused “cen/cep” pin. HS CIB can handle input signal amplitudes between 200mV and 1.2V p-p differential or single-ended. The buffer utilizes on-chip single-ended termination of 50Ohm to vcc for each input line.

CDR FWD

The Clock and Data Recovery Block (CDR FWD) contains both a phase and frequency acquisition loop that require a single off-chip filter featuring a 200Ohm resistor in series with a 1nF capacitor across the pins “ftr1” and “ftr2”. The frequency loop works in concert with “cr” while the phase loop utilizes “d”.

The main function of CDR FWD is to frequency lock the on-chip VCO to the input data signal (clock recovery) while phase aligning it to latch in the incoming data with minimal error (data recovery). The recovered clock is also utilized by /16 and DMX 1:16 to demultiplex the data.

CDR FWD raises the loss of signal “losn” flag when the input data’s quality in RZ format is not sufficient enough for an acceptable bit error rate or the transition density of the data in either format is not enough or too much. By default, CDR FWD is set for RZ input data (“offrz”=0) where “offrz” must set to logic “1” when there is input NRZ signaling. A loss of lock “loln” is generated by CDR FWD when the frequency difference between a processed “cr” and “C” divided-by-64 is greater than ±1000ppm.

/16

The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed clock “C” delivered by CDR FWD is fed into the first divide-by-2 where its output is routed internally to the next divide-by-two circuit and outside of the block to DMX1:16. Other divided down clock signals are formed and routed to DMX1:16 in similar fashion. Full rate clock divided-by-16 “C16” is passed on to CLK Proc for additional phase adjustment as well as directly to a LVDS OB.

DMX1:16

The 1 to 16 Demultiplexer (DMX1:16) utilizes a tree type architecture that latches in the data stream from CDR FWD on both edges of a half rate clock signal that is supplied by /16. The high speed data signal is subsequently demultiplexed down and delivered to LVDS DOBx16 in parallel fashion as16-bit wide words running at a data rate up to 780Mbps.

CLK Proc

By utilizing the CMOS control pins “phs1” and “phs2”, the phase of “clo” can be altered in accordance with the table below.

LVDS DOBx16

The LVDS Data Output Buffer (LVDS DOBx16) accepts 16-bit wide words from DMX1:16 and converts them into LVDS output signals. Each proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at bit rates up to 2Gb/s with a low power consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. When “bitordn”=0 (default), “q15”is the MSB and when “bitordn”=1, “q00” is designated the MSB.

LVDS COB x2

The dual LVDS Clock Output Buffer (LVDS COB x2) receives two clock signals and converts them into the LVDS output signals “clm” and “clo”. Each proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at frequencies up to 2GHz with a low power consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.

Pins diagram for asnt2011a-asnt2015 is not available.

The chip is packaged in a standard 100-pin QFN package.

Full package description: PDF

Full product description: PDF