ASNT2012 (2032)

• 1:16 demultiplexer (DMUX) with integrated full rate CDR (clock and data recovery)
• Supports multiple data rates in the 11.3-12.5Gbps range
• Supports NRZ input data format
• LVDS output data buffers that feature a low-power proprietary architecture
• Clock-divided-by-16 LVDS output buffer with 90°-step phase selection
• Single +3.3V power supply
• Industrial temperature range
• Low power consumption of 730mW at 12.5Gbps
• Available in standard 100-pin QFN package (12mm x 12mm)

ASNT2012 is a 12.5Gbps 1:16 deserializer (DMUX) with full rate integrated clock and data recovery (CDR). The DMUX can cover input data rates (fbit) from 11.3Gbps to 12.5Gbps by utilizing its on-chip full-rate VCO.

The main function of ASNT2012 is to demultiplex a serial input data channel “d” running at a bit rate of fbit into 16 parallel data channels “q00-q15” running at a bit rate of fbit/16. The high sensitivity CDR block ensures accurate clock and data recovery for input data signal amplitudes greater than 40mV peak to peak (p-p) differential or single-ended. This is accomplished with the CDR circuitry incorporating both a phase and frequency acquisition loop to recover a full rate clock “C” from the input data stream. This recovered clock is used to sample the input data bits before they are demultiplexed and provides a signal for the internal divider (/16). The application of an external low speed system clock “cmr” running at 1/16 the frequency of the VCO clock is required for CDR to operate correctly.

The high-speed CML data input buffer in CDR provides on-chip 50Ohm termination and is designed to be driven by devices with 50Ohm source impedance. The low speed clock input buffer (CLK IB) accepts the system reference clock “cmr” through a LVDS interface and delivers it to the CDR block.

The reconstructed serial input data is latched into the tree-type demultiplexer (DMX1:16) and subsequently deserialized and delivered to the demultiplexer’s output as 16-bit wide low-speed parallel words. Utilizing pin “bitordn”, the deserializer can designate either “q00” or “q15” as the MSB thus simplifying the interface between ASNT2012 and a following ASIC.

Sixteen proprietary low-power LVDS output data buffers (LVDS DOBx16) are used to deliver the 16 data output signals “q00-q15” while a similar LVDS clock output buffer (LVDS COB) outputs the low-speed clock signal “cls”. The buffers satisfy all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995 while only consuming 30mW each. The phase of “cls” can be modified by 90° increments by utilizing pins “phs1” and “phs2” and the low speed clock processing block (CLK Proc).

A loss of lock system signal alarm “lol” is generated by CDR. Off chip passive filter components are required by CDR and are connected through pins “ftr1/2”.

The deserializer uses a single +3.3V power supply and is characterized for operation from -25°C to 125°C of junction temperature.

CDR

The Clock and Data Recovery Block (CDR) contains both a phase and frequency acquisition loop that require an additional off-chip filter connected between the pins “ftr1p” and “ftr1n” (Fig. 2). The frequency loop works in concert with “cmr” while the phase loop utilizes “d”.

The main function of CDR is to frequency lock the on-chip VCO to the input data signal (clock recovery) while phase aligning it to latch in the incoming data with minimal error (data recovery). The recovered clock is also utilized by /16 and DMX 1:16 to demultiplex the data.

The lock detect circuitry signals an alarm through the CMOS signal “lol” when a frequency difference exists between the applied system reference clock “cmr” and recovered full rate clock divided-by-16 that is greater than ±1000ppm.

CLK IB

The Clock Input Buffer (CLK IB) consists of a proprietary universal input buffer (UIB) that exceeds the LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is designed to accept differential signals with amplitudes higher than 60mV p-p, DC common mode voltage variation between the negative (vee) and positive (vcc) supply rails, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of more than 60mV p-p and threshold voltages between vee and vcc. The input termination impedance is set to 100Ohm differential.

/16

The Divider-by-16 (/16) includes 4 divide-by-2 circuits connected in series. The high-speed clock “C” delivered by CDR is fed into the first divide-by-2 where its output is routed internally to the next divide-by-two circuit and outside of the block to DMX1:16. Other divided down clock signals are formed and routed to DMX1:16 in similar fashion. Full rate clock divided-by- 16 “C16” is passed on to CLK Proc for additional phase adjustment.

DMX1:16

The 1 to 16 Demultiplexer (DMX1:16) utilizes a tree type architecture that latches in the data stream from CDR on both edges of a half rate clock signal that is supplied by /16. The high speed data signal is subsequently demultiplexed down and delivered to LVDS DOBx16 in parallel fashion as16-bit wide words running at a data rate up to 780Mbps.

CLK Proc

By utilizing the CMOS control pins “phs1” and “phs2”, the phase of “cls” can be altered in accordance with the table below.

LVDS DOBx16

The LVDS Data Output Buffer (LVDS DOBx16) accepts 16-bit wide words from DMX1:16 and converts them into LVDS output signals. Each proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at bit rates up to 2Gb/s with a low power consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3- 1996 and ANSI/TIA/EIA-644-1995. When “bitorder”=0 (default), “q00”is the MSB and when “bitorder”=1, “q15” is designated the MSB.

LVDS COB

The LVDS Clock Output Buffer (LVDS COB) receives “C16” from CLK Proc and converts it into the LVDS output signal “cls”. The proprietary low-power LVDS output buffer utilizes a special architecture that ensures operation at frequencies up to 2GHz with a low power consumption level of 30mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3- 1996 and ANSI/TIA/EIA-644-1995.

Pins diagram for asnt2012-2032 is not available.

The chip is packaged in a standard 100-pin QFN package.

Full package description: PDF

Full product description: PDF