ASNT2112-KMF

• 1:2 demultiplexer (DMUX) with integrated full-rate CDR (clock and data recovery)
• Supports a wide frequency range digital mode or CDR mode from 21.5GHz to 25.6GHz
• Can process RZ and NRZ input data formats
• Adjustable data time sampling point for optimum BER performance
• Full rate retimed data output available for 1:1 CDR operation
• Half rate data outputs support toggle synchronization functionality
• All output buffers have signal inversion and muting capabilities
• Single +3.3V power supply
• Industrial temperature range
• Low power consumption of 1.4W at 25.6Gbps
• Available in custom leaded 64-pin metal ceramic package

ASNT2112 is a 1:2 deserializer (DMUX) with full rate integrated clock and data recovery (CDR). The DMUX can function at input data rates (fbit) from 21.5Gbps up to 25.6Gbps by utilizing its multiple on-chip full-rate VCOs or in a broadband (DC to 25.6Gbps) digital mode. An external full clock “ce” must be applied to the high speed clock input buffer (HS CIB) for digital operation. Selection of the desired working data rate and mode is accomplished through pins “vcos0” and “vcos1” (see the Table in CDR section below).

The main function of ASNT2112 is to demultiplex a serial input data channel “d” running at a bit rate of fbit into 2 parallel NRZ data channels “q0” and “q1” running at bit rates of fbit/2. A full rate retimed NRZ data output signal “do” is made available through the data output buffer (DOB) allowing ASNT2110 to be used as a 1:1 CDR. Half rate clock “c2” is supplied with tight phase alignment to the two demultiplexed data outputs through the clock output buffer (COB).

The high sensitivity data input buffer (Data IB) in unison with the CDR ensures accurate clock and data recovery for input data signals in either the RZ or NRZ format with amplitudes greater than 50mV peak to peak (p-p) differential or single-ended. This is accomplished with a combination of Data IB having high gain while delivering 30GHz of analog bandwidth and the CDR circuitry incorporating both a phase and frequency acquisition loop to recover a full rate clock from the input data stream. This recovered clock is used to sample the input data bits before they are demultiplexed while its phase can be adjusted externally through pin “phshft” to locate the optimum sampling point to achieve the lowest system bit error rate. The application of an external low speed system clock “c32” running at 1/32 the frequency of the active VCO is required for CDR to operate correctly

Data IB is a high-speed differential CML buffer providing on-chip 50 Ohm termination and is designed to be driven by devices with 50 Ohm source impedance. The threshold tuning pins “dcinp/n” provide proper offset adjustment when the buffer is operating with single ended input signaling. A peak detector is also included to provide means of demodulating any AM components carried by “d” that range in frequency up to a few hundred KHz. Results of the peak detector are delivered by the differential signal “pkdt”.

The low speed clock input buffer (CLK IB) accepts the system reference clock “c32” through a fully LVDS compliant interface and delivers it to CDR. All output buffers provide CML signaling and are back terminated with 50Ohms. DOB, COB, and the two half rate data output buffers (D2OBx2) can be individually diabled through pins “ondo”, “onco”, and “ond2o” to save power.

Utilizing pin “pol”, the deserializer can invert the polarity of the three output data signals. Pin “tog” flips the order of “q0” and “q1” thus simplifying the interface between ASNT2112 and a following ASIC. It also can function as a way to synchronize the bit order of two or more ASNT2112s working in parallel.

A loss of lock 2.5V CMOS alarm signal “lolp” is generated by CDR. Off chip passive filter components are required by CDR and are connected through the pin “ftr”.

The deserializer uses a single +3.3V power supply and is characterized for operation from −5°C to 125°C of junction temperature. Its temperature resistance is 15°C/W.

Data IB

The Data Input Buffer (Data IB) can process an input CML data signal “d” with bit rates up to 25.6Gbps in either the RZ or NRZ format due to its 30GHz of analog bandwidth. It can also accept a single-ended signal to one of its input ports “dp” or “dn” with a threshold voltage applied to the opposite tuning pin “dcinn” or “dcinp”. The tuning pins have input impedances of 1KOhm and allow the user to change the slicing level before the data is sampled by the recovered clock. A tuning voltage from positive (Vcc) to negative (Vee) supply rail delivers Vcc-150mV of input port DC voltage shift. Data IB can handle input signal amplitudes between 50mV and 600mV p-p differential or single-ended. The buffer utilizes on-chip single-ended termination of 50Ohm to Vcc for each input line.

Also included in Data IB is an input signal peak detector that delivers its response through the output differential signal “pkdt”. The detector can demodulate AM component(s) carried by the input data stream that are in the frequency range of up to a few hundred kHz. The peak detector’s output impedance is 4KOhm single ended to Vcc.

HS CIB

The High-Speed Clock Input Buffer (HS CIB) can process an external CML clock signal “ce” with frequencies from 10MHz to 31GHz. It can also accept a single-ended signal to one of its pins with a threshold voltage applied to the unused pin. HS CIB can handle input signal amplitudes between 200mV and 1.2V p-p differential or single-ended. The buffer utilizes on-chip single-ended termination of 50Ohm to Vcc for each input line.

CLK IB

The Clock Input Buffer (CLK IB) consists of a proprietary universal input buffer (UIB) that exceeds the LVDS standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. UIB is designed to accept differential signals running at frequencies up to 1GHz with amplitudes higher than 60mV p-p, DC common mode voltage variation between Vcc and Vee, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of more than 60mV p-p and threshold voltages between Vcc and Vee. The input termination impedance is set to 100Ohm differential.

CDR

The Clock and Data Recovery Block (CDR) contains both a phase and frequency acquisition loop that require a single off-chip filter connected to the pin “ftr”. The frequency loop works in concert with “c32” while the phase loop utilizes “d”.

The main function of CDR is to frequency lock the on-chip active VCO to the input data signal (clock recovery) while phase aligning it to latch in the incoming data with minimal error (data recovery). By default, CDR aligns the recovered clock’s working edge in the middle of the incoming data bits. Pin “phshft” can be utilized to shift this position from one edge of the data bit to the other (±30ps) in order to locate the optimum sampling point to generate the lowest system BER. The recovered clock is divided down in frequency by two “C2” and utilized by DMX 1:2 to demultiplex the recovered data.

By utilizing the CMOS control pins “vcos0” and “vcos1”, the desired working frequency of CDR can be selected in accordance with the table below.

The lock detect circuitry signals an alarm through the CMOS signal “lolp” when a frequency difference exists between the applied system reference clock “c32” and recovered full rate clock divided-by-32 that is greater than ±1000ppm.

Another feature included in CDR is the ability to simultaneously invert the polarity of all three data outputs through CMOS input pin “pol” (“pol”=1 (default), direct; “pol”=0, inverted). The half rate output data streams can be switched by using the CMOS input pin “tog”. “tog” provides a means to synchronize two adjacent ASNT2112s operating in parallel. The synchronization process may be accomplished by the “blind” toggling of a single ASNT2112 and leaving the task of recognizing the “right” position by downstream components (e.g. FEC chip).

DMX1:2

The 1 to 2 Demultiplexer (DMX1:2) latches in the retimed data stream “D” from CDR on both edges of the half rate clock signal “C2”. The high speed data signal is subsequently demultiplexed into two half rate NRZ data signals and delivered to D2OBx2 in parallel fashion as 2-bit wide words running at a data rate up to 12.8Gbps.

DOB

The Data Output Buffer (DOB) receives the full rate retimed serial data stream “D” from CDR and converts it into the CML output signal “do” with a single ended swing of 400mV. The buffer requires 50Ohm external termination resistors connected between “vcc” and each output to match its internal 50Ohm resistors and can operate at a data rate up to 25.6Gbps. The buffer can be enabled or disabled by the external 2-state CMOS control signal “ondo”. The logic “0” state disables the buffer completely to save power while the logic “1” state (default) provides a full rate data output.

D2OBx2

The Half Rate Data Output Buffer (D2OBx2) receives two half rate data signals from DMX1:2 and converts them into CML output signals “q0” and “q1” with single ended swings of 400mV. The buffer requires 50Ohm external termination resistors connected between “vcc” and each output to match its internal 50Ohm resistors and can operate at a data rate up to 12.8Gbps. The buffer can be enabled or disabled by the external 2-state CMOS control signal “ond2o”. The logic “0” state disables the buffer completely to save power while the default logic “1” state (default) provides the two half rate data outputs.

COB

The Clock Output Buffer (DOB) receives a half rate clock signal from DMX1:2 and converts it into the CML output signal “c2” with a single ended swing of 400mV. The buffer requires 50Ohm external termination resistors connected between “vcc” and each output to match its internal 50Ohm resistors and can operate at a data rate up to 12.8GHz. The buffer can be enabled or disabled by the external 2-state CMOS control signal “onco”. The logic “0” state disables the buffer completely to save power while the logic “1” state (default) provides a half rate clock output. COB is designed so “c2”’s negative edge is aligned to the half rate output data crossing points.

Absolute Maximum Ratings

Caution: Exceeding the absolute maximum ratings may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground.

The chip is packaged in a standard metal-ceramic-64-pin QFN package.

Full package description: PDF

Full product description: PDF