ASNT3010_QQB

• 2-channel LVDS-to-CMOS converter (Receiver).
• 2-channel CMOS-to-LVDS converter (Transmitter).
• Triple-action programmable LVDS/CML/ECL inputs.
• Optional DS (Data/Strobe) encoding/decoding for compatibility with Space Wire Standard.
• Optional signal splitter function with selectable inversion.
• Flexible selection of channels enabling and operational modes.
• High-impedance states of disabled CMOS outputs.
• Single +3.3V power supply.
• Industrial temperature range.
• Power consumption: 115mW with all 4 channels enabled.
• Package: 40-pin MLF with 6x6mm2 body size and 0.5mm lead pitch.

ASNT3010 is a bi-directional 4-channel digital interface converter. It includes two independent “Receiver” channels with programmable LVDS/CML/ECL differential inputs (“d1p/n”, “d2p/n”) and CMOS outputs (“qm1’, “qm2”), as well as two reverse “Transmitter” channels with CMOS inputs (”dm1”, “dm2”) and LVDS differential outputs (“q1p/n”, “q2p/n”).

All channels can be independently enabled or disabled by control signals (“crlr1”, “crlr2”, “crlt1”, “crlt2”). When disabled, the CMOS output drivers are set to a high impedance (high-Z) state. Both receiver and transmitter channel pairs can be combined into a Space Wire receiver/transmitter with optional data/strobe (DS) encoding or decoding. The assignment of data and strobe or data and clock signals to the individual channels is user-selectable.

Dual transmitter and/or receiver channels can be used for splitting one of the input signals into two exact copies at two corresponding outputs. The signal at the second output can be inverted using the second input as a selector (a differential DC signal must be applied). Detailed instructions for using this operational mode are available on request.

The converter operates at data rates up to 2Gbps with a nominal power consumption of 115mW from a single +3.3V power supply in a fully activated mode. The device is characterized for operation from −25°C to 125°C of junction temperature.

The converter has an improved TID tolerance due to the HBT-based implementation.

Universal IB

The proprietary Universal Input Buffer (UIB) is designed to accept differential signals with amplitudes higher than 60mV, DC common mode voltage variation between the negative and positive supply voltages, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. It can also receive single-ended signals with amplitudes of more than 60mV and threshold voltages between the negative and positive supply rails. The buffer outputs standard internal CML signals with amplitude of 220mV. The buffer features a reconfigurable input block with internal LVDS, CML, or ECL termination that is controlled by two external CMOS signals “oncml” and “onecl” in accordance with the following table.

The ECL termination mode requires an external termination voltage of VECL=VCC-2V applied to the pins labeled “vecl”. The buffer is set to work with incoming LVDS data by default.

CML-to-CMOS Converter

The CML-to-CMOS converter represents the output buffer of the Receiver. It includes a signal converter based on the current mirror architecture and an output CMOS driver. The block designed in a BiCMOS configuration operates at a data rate up to 2Gbps.

CMOS-to-CML Converter

The input CMOS-to-CML converter represents the input buffer of the Transmitter. It is designed as a standard CML buffer with additional resistive dividers required for the handling of rail-torail CMOS signals.

LVDS Output Buffer

The proprietary LVDS output buffer utilizes NPN HBTs that are available in standard BiCMOS technologies. It accepts the internal CML signals and converts them into output LVDS signals. The buffert utilizes a special architecture that ensures operation at data rates up to 2Gbps with a low power consumption level of 19mW. The buffer satisfies all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995.

Internal Data Processing Circuitry

The internal parts of all 4 channels include an XOR and multiplexer 2:1 CML cells. When activated, the XOR performs the DS encoding or decoding required by the Space Wire protocol, while the multiplexer operates as a selector between the channel’s input signal or XORprocessed signals. The corresponding control signals are generated by the receiver or transmitter control blocks (RCB or TCB) from 3-state external activation control signals.

Each channel can function as an independent converter, as well as a data/strobe or clock/strobe Space Wire encoder/decoder in accordance with the following table. In the second mode, the device can also perform the 1-to-2 data splitting operation (described in Application notes).

The chip is packaged in a standard 40-pin QFN package.

Full package description: PDF

Full product description: PDF