ASNT8010
17GHz Programmable Integer Divider
- Wide frequency range from DC to 17GHz
- Contiguous division ratios from 1 to 256
- 50% duty cycle of the divided clock signal
- Differential or single-ended CML input interface with on-chip 50ohm termination to the positive supply rail (“vcc”)
- Differential or single-ended CML output interface with on-chip 50ohm termination to the positive supply rail (“vcc”)
- Easy 8-bit parallel programming interface compatible with LVTTL or 3.3V CMOS standards
- Optional external reset function
- Optional dynamic mode of the division ratio adjustment with a short set-up time (about 20ns after the pulse edge on any control input)
- Single 2.5...3.5V power supply
- Industrial temperature range
- Current consumption of 950mA at full operational speed
- Standard 40-pin QFN package with a thermal pad
ASNT8010 is a high-speed programmable integer clock divider with static or dynamic adjustment of the division ratio through the standard 8-bit parallel LVTTL/CMOS interface and optional external reset (active-high 3.3V CMOS/LVTTL signal). The device automatically resets itself after the initial power-up and any change of the division control signals. When optional external reset signal (“reset”) is set to “high”, ASNT8010 switches to idle (static “0” output) after a 0.7ns delay as shown in the timing diagram below. When “reset” returns to “low”, the divider switches back to normal operation after (64...128) periods of the high-speed system clock plus additional 1.6ns delay. The minimum allowed “reset” pulse must not be shorter than 64 periods of the high-speed system clock.
The divider accepts the input clock signal (“chip/chin”) with a speed from DC to 17GHz and provides a clean 50% duty cycle output signal (“cop/con”) in any operational mode. The utilized input and output buffers are fully compatible with the CML interface. They feature internal 50Ohm termination to the positive supply rail (“vcc”) and support both differential (DC or AC) and single-ended (AC) termination modes. The external transmission media can be a printed circuit board or copper coaxial cables with a 50Ohm impedance.
ASNT8010 allows for both static and dynamic adjustment of the division ratio from 1 to 256 with a step of 1. In the static mode, the binary code on the control inputs “C0”-“C7” defines the value of the ratio from 1 to 255, where “C7” is the most significant bit. All “0”s (“low” state) define the division by 256. Following any change of a control signal in the dynamic mode, the divider switches to idle after (64...128) periods of the high-speed system clock plus additional 1.6ns delay, and returns back to normal operation with the new division ratio after additional delay equal to 192 periods of the high-speed system clock.
ASNT8010 uses a positive 3.3V power supply with “vee” as a ground node and is characterized for operation at -25°C to 125°C of junction temperatures. It can also operate from a negative 3.3V supply voltage with “vcc” as a ground node and the appropriate correction of the control signals.
The device is packaged into a standard 40-pin QFN plastic package with a bottom thermal pad.
APPLICATION
ASNT8010 can be used as a general-purpose reprogrammable divider in a variety of high- frequency synthesizer applications. It is particularly suitable for the advanced measurement equipment.
PCB DESIGN RECOMMENDATIONS
- ASNT8010 requires a 50Ohm impedance environment for clock input and output signals.
- Pins No. 19, 33, 35, 37, and 39 must be kept OPEN (not connected)!
- One external capacitor of 47nF must be inserted between pin No. 9 and the ground plane.
- Additional heat sink is recommended for the reliable operation.
Electrical diagram for asnt8010 is not available.
The chip is packaged in a standard 40-pin QFN package.
Full package description: PDF
Full product description: PDF