12:24 LVDS-LVDS Demultiplexer

Digital demultiplexer (DMUX) 12-to-24 with LVDS output interface
Programmable LVDS/CML/ECL input interface
Supports data rates from 1.0Mbps to 3.6Gbps
Preset function for synchronization of multiple parallel devices
Two pairs of clock divided-by-2 and synchronous clock enable outputs for supporting a tree-type demultiplexation structure
Selectable clock divided-by-4 or divided-by-2 output
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Frequency (min): 1.0 Mbps
Frequency (max): 3.6 Gbps
Power: 924 mW
Package: 256-pin BGA
Price: Request

Product Details

Fig. 1. Functional Block Diagram

ASNT2032-MBL is a broadband multichannel digital deserializer/demultiplexer (DMUX) 12-to-24 with an external initial preset function, selectable LVDS, CML or ECL input interface, and LVDS output interface. The part  also features selectable clock divided-by-2 or clock divided-by-4 outputs with multiple phases. The latter is intended for DDR interface support.


The operational speed of the DMUX is defined by an external clock signal (cip/cin) that is converted into required timing signals by the internal divider. The divider can be preset to a certain initial state by an external active-low reset signal (rnp/rnn), which allows synchronization of multiple DMUX devices operating in parallel. The reset signal is retimed inside the chip by the external clock and its positive edge must satisfy the timing shown in Fig. 3 within the part’s datasheet. The position of the reset signal’s negative edge is not important. This part also supports cascaded tree-type structures as shown in Fig. 5 within the part’s datasheet, by supplying two synchronous copies of clock divided-by-2 (co1p/co1n and co2p/co2n) and clock enable (rno1p/rno1n and rno2p/rno2n) signals. The  IC uses one positive power supply vcc = +3.3V and is characterized for operation from −25°C to 125°C of junction temperature.