4-bit Flash Analog-to-Digital Converter with 20GHz Input Analog Bandwidth

20GHz analog input bandwidth
Selectable clocking mode: external high-speed clock or internal PLL with external reference clock
Broadband operation in external clocking mode: DC-15GS/s
On-chip PLL with a central frequency of 10GHz
Optional external preset of the internal clock divider
Internal demultiplexer 4-to-16 for the output data rate reduction
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Frequency (min): DC
Frequency (max): 20 GHz
Power: 3570 mW
Package: 100-pin CQFP
Price: Request

Product Details

asnt7120a-kma desc

Fig. 1 Functional Block Diagram

The ASNT7120A-KMA is a 4-bit flash analog to digital converter (ADC) featuring a high sampling rate and wide analog front-end bandwidth. The ADC system shown in Fig. 1 includes a linear input buffer (LIB) with tree-type architecture and a CML-type input interface with internal 50Ohm single-ended terminations to vcc. The buffer delivers 15 matching copies of the input analog data signal dp/dn to the 4-bit flash ADC. The ADC creates 15 samples of the input data in thermometer code, which are then converted by a thermometer-to-binary encoder (TTB Encoder) into 4-bit binary words with a data rate f. The ADC thresholds are controlled by signals vrefcrl and vlsbcrl. The encoded data is demultiplexed into 16-bit wide words with a data rate f/4 and sent to the output through 16 low-power LVDS buffers as signals q00p/q00n–q15p/q15n. An optional digital-to-analog converter (DAC) with an output signal odp/odn can be used to control the ADC’s operation. It is enabled by using control signal ondac.

All operations are synchronized by the internal clock multiplication unit (CMU) based on aPLL(phase-locked loop) with an integrated divider and an external loop filter connected to pin ftr. The block can operate in two different modes which are controlled by signal ceoff: clock multiplication (PLL is on, a reference clock is applied to pins crp/crn), and clock division (PLL is off, an external high-speed clock is applied to pins cep/cen). In both modes, the divider generates internal clock signals divided by 2, 4, 8, and 16. The generated divided clocks are sent to different internal blocks. In the CMU’s second operational mode, the divider can be preset by external signal res to allow synchronization of parallel-connected ADCs. A PLL lock control output lol is also provided. The part operates from a single +3.5V power supply. All external control signals are compatible with the 2.5CMOS interface.