Fig. 1 Functional Block Diagram
ASNT8131-PQC is a high-speed, low-power divider by-2 and by-4 with increased sensitivity. The part shown in Fig. 1 accepts a CML input clock signal (cp/cn) with the speed from DC to maximum operational frequency and provides clean 50% duty cycle output signals with divided-by-2 (c2p/c2n) and divided-by-4 (c4p/c4n) frequency. The part’s I/Os support the CML logic interface with on chip 50Ohm termination to vcc and may be used differentially, AC/DC coupled, single-ended, or in any combination. It operates from a single +3.3V or -3.3V power supply.