Fig. 1 Functional Block Diagram
The ASNT8141-KMC SiGe IC provides a 127-bit full length pseudo-random binary sequence (PRBS) according to polynomial (x7 + x6 + 1), where xD represents a delay of D clock cycles. This is implemented with a linear feedback shift register (LFSR) in which the outputs of the seventh and first flip-flops are combined together by XOR function and provided as an input to the first flip-flop of the register.
The LFSR-based PRBS generator produces 127 binary states, excluding the “all zeros” state that is illegal for the XOR-based configuration. To eliminate this state that locks the LFSR and prevents the PRBS generation, an asynchronous external active-low preset signal rstn_p/rstn_n is implemented in the circuit. When the preset is asserted, LFSR is set to the “1000000” state containing one logic “1” value that is enough for the activation of the PRBS generation. When the preset is released, the chip delivers one consecutive bit of the PRBS signal to output pins qp/qn per each rising edge of clock clk_p/clk_n, starting from the above mentioned state.
An additional copy of the same PRBS signal delayed by 63 bits (half of the sequence period) is delivered to pins qxorp/qxorn and can be used to double the frequency of the output signal using an external multiplexer. All I/O stages are back terminated to vcc with on-chip 50Ω resistors and may be used in either DC or AC coupling modes. In the first mode, the input signal’s common mode voltage should comply with the specifications shown in the electrical characteristics section of the part’s datasheet. In the second mode, the input termination provides the required common mode voltage automatically. The differential DC signaling mode is recommended for optimal performance, and the part operates from a single +3.3V or -3.3V power supply.